1. Field of the Invention
The present invention relates to a semiconductor memory and more specifically to a semiconductor memory wherein a three-dimensional structure in which a capacitor is laminated on a transistor formed on a surface of a semiconductor substrate, i.e., a stack structure is formed so that an area of a memory cell is made smaller as compared with a case in which the transistor and the capacitor are simply arranged on the surface of the semiconductor substrate in a plane, and in particular, to a semiconductor memory which is useful for increasing a capacity of a capacitor of a DRAM (dynamic random access memory) of which memory cell has a reduced area in order to make integration higher.
2. Description of the Prior Art
Conventionally, there has been proposed a DRAM (dynamic random access memory) shown in FIGS. 5 or 6 as a semiconductor memory having a stack structure of the above type.
The DRAM shown in FIG. 5 has two memory cells (M3) and (M4) provided on a surface of a semiconductor substrate (21). The memory cells (M3) and (M4) are adjacent to each other and have structures symmetrical relative to a bit line (BL). The memory cell (M3) includes a transistor (Tr3) and a capacitor (C3) formed on the transistor (Tr3). The transistor (Tr3) has a drain (24) which is connected to the bit line (BL) through a contact portion (24a), a source (25) which is provided on an oxide film (31) for device isolation side, and a gate oxide film (22) and a gate electrode (23) which cover a region between the drain (24) and the source (25). The capacitor (C3) has a node polysilicon electrode (27) comprised of a node portion (27a) and vane portions (27b) and (27c), an insulating film (28) and a plate electrode (29) which has portions opposite to the node and vane portions of the node polysilicon electrode (27) with the insulating film (28) interposed. The node portion (27a) is connected to the source (25). The vane portion (27b) is extended over the transistor (Tr3), while the vane portion (27c) is extended over a polysilicon wire (32). Thus, a three-dimensional structure (stack structure) in which the capacitor (C3) is laminated on the transistor (Tr3) is formed, so that an area of the memory cell is made smaller as compared with a case in which the transistor (Tr3) and the capacitor (C3) are simply arranged on the surface of the semiconductor substrate (21) in a plane. The reference numerals (26), (30) and (33) denote layer insulating films. A drain (34) of a transistor (Tr4) of the memory cell (M4) is common to the drain (24) of the transistor (Tr3).
A DRAM shown in FIG. 6 comprises two memory cells (M5) and (M6) which are adjacent to each other and have structures symmetrical relative to the contact portion (24a) of the bit line (BL) in similar to the DRAM shown in FIG. 5. The memory cell (M5) includes a transistor (Tr5) and a capacitor (C5). The memory cell (M6) includes a transistor (Tr6) and a capacitor (C6). The capacitors (C5) and (C6) have structures symmetrical to each other. For example, a node polysilicon electrode (47) of the capacitor (C5) has a node portion (47a) which is perpendicular to a surface of a substrate (41), and a pair of vane portions (47b) and (47c) and a pair of vane portions (47d) and (47e). The vane portions (47b) and (47c), and (47d) and (47e) cross the node portion (47a) and have two layers which are almost parallel with the surface of the substrate (41) in up and down directions, respectively. The node portion (47a) is connected to a source (45). The vane portions (47d) and (47e) are extended over the transistor (Tr5). The vane portions (47b) and (47c) are extended over the polysilicon wire (32). A plate electrode (49) is opposed to the node portion (47a) and vane portions (47b), (47c), (47d) and (47e) of the node polysilicon electrode (47) through an insulating film (48) shown in a heavy line of FIG. 6. Thus, the transistor (Tr5) and the capacitor (C5) have a stack structure in similar to the DRAM shown in FIG. 5, so that the area of the memory cell is reduced. Furthermore, since the electrodes (47) and (49) of the capacitor (C5) are opposed to each other through the insulating film (48), electrode opposed areas of the electrodes (47) and (49) are made larger so as to increase a capacity.
However, if the area of the memory cell is reduced in order to make integration higher in the conventional DRAM, the memory cells shown in FIGS. 5 and 6 cause the electrode opposed areas of the capacitors to be reduced. Consequently, there is caused a problem that the capacity of the capacitor becomes insufficient.
It is an object of the present invention to provide a semiconductor memory capable of keeping a larger electrode opposed area of a capacitor forming a memory cell so as to keep a larger capacity of the capacitor even if an area of the memory cell is reduced in order to make the integration higher.